該怎樣控制 LED  由 暗(0%)  慢慢到 最亮(100%)
暗(0%) 慢慢到 最亮(100%) 整個過程時間大約2S,

LED掃瞄頻率由慢調快即可.

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走是為了到另一境界，停是為了欣賞人生；未走過千山萬水，怎知生命的虛實與輕重！？

您好
可以用PWM,然後在兩秒內去分配你要控制的亮度

參考看看，裡面很亂
-- ********************************************** --
-- Function's --
-- 1. DIP switch set Left/Right & Fast/Meed/Slow --
-- states. --
-- 2. 7 Segment display 24hour's TIME. --
-- 3. 8 LED's show PWM demo. --
-- ********************************************** --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_SET : in STD_LOGIC_VECTOR (7 downto 0); -- DIP switch
D_BUS : out STD_LOGIC_VECTOR (7 downto 0); -- 7 segment display : a~g
SCAN : out STD_LOGIC_VECTOR (7 downto 0); -- 7 segment display : scan
PWM_OUT : out STD_LOGIC_VECTOR (7 downto 0) -- 8 LED's PWM output
);
end PWM;
architecture Behavioral of PWM is
-- Clock generater
signal DEVIDER : STD_LOGIC_VECTOR (24 downto 0) := (others => '0');
-- Reset debounce
signal RST_DB : STD_LOGIC;
-- All triger's
signal F_triger : STD_LOGIC; -- PILI light clock
signal T_triger : STD_LOGIC; -- PWM step inc
signal S_triger : STD_LOGIC; -- 7 segment display scan triger
-- 7 segment display
signal CLK_1 : STD_LOGIC;
signal min : STD_LOGIC := '0';
signal hour : STD_LOGIC := '0';
signal S_scan : STD_LOGIC_VECTOR (7 downto 0) := "11111110";
signal data : STD_LOGIC_VECTOR (7 downto 0);
signal D_BCD : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
-- PWM 寬度設定
signal triger : STD_LOGIC_VECTOR (7 downto 0);
signal T_cmp1 : STD_LOGIC_VECTOR (7 downto 0); -- D 14 X"FF"
signal T_cmp2 : STD_LOGIC_VECTOR (7 downto 0); -- D 13 x"DD"
signal T_cmp3 : STD_LOGIC_VECTOR (7 downto 0); -- D 12 x"99"
signal T_cmp4 : STD_LOGIC_VECTOR (7 downto 0); -- D 11 x"77"
signal T_cmp5 : STD_LOGIC_VECTOR (7 downto 0); -- D 10 x"55"
signal T_cmp6 : STD_LOGIC_VECTOR (7 downto 0); -- D 9 x"33"
signal T_cmp7 : STD_LOGIC_VECTOR (7 downto 0); -- D 8 x"11"
signal T_cmp8 : STD_LOGIC_VECTOR (7 downto 0); -- D 7 X"00"
-- PWM 計數
signal T_on1 : STD_LOGIC_VECTOR (7 downto 0);
signal T_on2 : STD_LOGIC_VECTOR (7 downto 0);
signal T_on3 : STD_LOGIC_VECTOR (7 downto 0);
signal T_on4 : STD_LOGIC_VECTOR (7 downto 0);
signal T_on5 : STD_LOGIC_VECTOR (7 downto 0);
signal T_on6 : STD_LOGIC_VECTOR (7 downto 0);
signal T_on7 : STD_LOGIC_VECTOR (7 downto 0);
signal T_on8 : STD_LOGIC_VECTOR (7 downto 0);
-- PILI LIGHT
signal PILI : STD_LOGIC_VECTOR (7 downto 0) := "11111110";
begin
-- PWM 計數
-- PILI Light rotate
process(RST_DB,T_triger)
begin
if RST_DB = '0' then
PILI <= "11111110";
T_cmp1 <= x"00";
T_cmp2 <= x"00";
T_cmp3 <= x"00";
T_cmp4 <= x"00";
T_cmp5 <= x"00";
T_cmp6 <= x"00";
T_cmp7 <= x"00";
T_cmp8 <= x"00";
elsif rising_edge(T_triger) then -- Left
if CLK_SET(7) = '0' then
PILI <= PILI(6 downto 0) & PILI(7);
elsif CLK_SET(6) = '0' then -- Right
PILI <= PILI(0) & PILI(7 downto 1);
end if;
if CLK_SET(7) = '0' then
case PILI is
when "11111110" =>
T_cmp1 <= x"80"; -- D 14
T_cmp2 <= x"DD"; -- D 13
T_cmp3 <= x"EE"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"00"; -- D 7
when "11111101" =>
T_cmp1 <= x"DD"; -- D 14
T_cmp2 <= x"EE"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"00"; -- D 8
T_cmp8 <= x"80"; -- D 7
when "11111011" =>
T_cmp1 <= x"EE"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"00"; -- D 9
T_cmp7 <= x"80"; -- D 8
T_cmp8 <= x"DD"; -- D 7
when "11110111" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"00"; -- D 10
T_cmp6 <= x"80"; -- D 9
T_cmp7 <= x"DD"; -- D 8
T_cmp8 <= x"EE"; -- D 7
when "11101111" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"00"; -- D 11
T_cmp5 <= x"80"; -- D 10
T_cmp6 <= x"DD"; -- D 9
T_cmp7 <= x"EE"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when "11011111" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"00"; -- D 12
T_cmp4 <= x"80"; -- D 11
T_cmp5 <= x"DD"; -- D 10
T_cmp6 <= x"EE"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when "10111111" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"00"; -- D 13
T_cmp3 <= x"80"; -- D 12
T_cmp4 <= x"DD"; -- D 11
T_cmp5 <= x"EE"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when "01111111" =>
T_cmp1 <= x"00"; -- D 14
T_cmp2 <= x"80"; -- D 13
T_cmp3 <= x"DD"; -- D 12
T_cmp4 <= x"EE"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when others => null;
end case;
elsif CLK_SET(6) = '0' then
case PILI is
when "01111111" =>
T_cmp1 <= x"00"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"EE"; -- D 9
T_cmp7 <= x"DD"; -- D 8
T_cmp8 <= x"80"; -- D 7
when "10111111" =>
T_cmp1 <= x"80"; -- D 14
T_cmp2 <= x"00"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"EE"; -- D 8
T_cmp8 <= x"DD"; -- D 7
when "11011111" =>
T_cmp1 <= x"DD"; -- D 14
T_cmp2 <= x"80"; -- D 13
T_cmp3 <= x"00"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"EE"; -- D 7
when "11101111" =>
T_cmp1 <= x"EE"; -- D 14
T_cmp2 <= x"DD"; -- D 13
T_cmp3 <= x"80"; -- D 12
T_cmp4 <= x"00"; -- D 11
T_cmp5 <= x"FF"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when "11110111" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"EE"; -- D 13
T_cmp3 <= x"DD"; -- D 12
T_cmp4 <= x"80"; -- D 11
T_cmp5 <= x"00"; -- D 10
T_cmp6 <= x"FF"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when "11111011" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"EE"; -- D 12
T_cmp4 <= x"DD"; -- D 11
T_cmp5 <= x"80"; -- D 10
T_cmp6 <= x"00"; -- D 9
T_cmp7 <= x"FF"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when "11111101" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"EE"; -- D 11
T_cmp5 <= x"DD"; -- D 10
T_cmp6 <= x"80"; -- D 9
T_cmp7 <= x"00"; -- D 8
T_cmp8 <= x"FF"; -- D 7
when "11111110" =>
T_cmp1 <= x"FF"; -- D 14
T_cmp2 <= x"FF"; -- D 13
T_cmp3 <= x"FF"; -- D 12
T_cmp4 <= x"FF"; -- D 11
T_cmp5 <= x"EE"; -- D 10
T_cmp6 <= x"DD"; -- D 9
T_cmp7 <= x"80"; -- D 8
T_cmp8 <= x"00"; -- D 7
when others => null;
end case;
elsif CLK_SET(7 downto 6) = "00" or CLK_SET(7 downto 6) = "11" then
T_cmp1 <= x"80"; -- D 14
T_cmp2 <= x"80"; -- D 13
T_cmp3 <= x"80"; -- D 12
T_cmp4 <= x"80"; -- D 11
T_cmp5 <= x"80"; -- D 10
T_cmp6 <= x"80"; -- D 9
T_cmp7 <= x"80"; -- D 8
T_cmp8 <= x"80"; -- D 7
end if;
end if;
end process;
-- PWM Cycle time
period:
process(CLK,RST_DB)
begin
if RST_DB = '0' then
triger <= (others => '0');
T_on1 <= (others => '0');
T_on2 <= (others => '0');
T_on3 <= (others => '0');
T_on4 <= (others => '0');
T_on5 <= (others => '0');
T_on6 <= (others => '0');
T_on7 <= (others => '0');
T_on8 <= (others => '0');
elsif rising_edge(CLK) then
T_on1 <= T_on1 1;
T_on2 <= T_on2 1;
T_on3 <= T_on3 1;
T_on4 <= T_on4 1;
T_on5 <= T_on5 1;
T_on6 <= T_on6 1;
T_on7 <= T_on7 1;
T_on8 <= T_on8 1;
-- CH1 PWM
if T_on1 <= T_cmp1 then
triger(0) <= '1';
else
triger(0) <= '0';
end if;
if T_on1 = x"FF" then
T_on1 <= (others => '0');
end if;
-- CH2 PWM
if T_on2 <= T_cmp2 then
triger(1) <= '1';
else
triger(1) <= '0';
end if;
if T_on2 = x"FF" then
T_on2 <= (others => '0');
end if;
-- CH3 PWM
if T_on3 <= T_cmp3 then
triger(2) <= '1';
else
triger(2) <= '0';
end if;
if T_on3 = x"FF" then
T_on3 <= (others => '0');
end if;
-- CH4 PWM
if T_on4 <= T_cmp4 then
triger(3) <= '1';
else
triger(3) <= '0';
end if;
if T_on4 = x"FF" then
T_on4 <= (others => '0');
end if;
-- CH5 PWM
if T_on5 <= T_cmp5 then
triger(4) <= '1';
else
triger(4) <= '0';
end if;
if T_on5 = x"FF" then
T_on5 <= (others => '0');
end if;
-- CH6 PWM
if T_on6 <= T_cmp6 then
triger(5) <= '1';
else
triger(5) <= '0';
end if;
if T_on6 = x"FF" then
T_on6 <= (others => '0');
end if;
-- CH7 PWM
if T_on7 <= T_cmp7 then
triger(6) <= '1';
else
triger(6) <= '0';
end if;
if T_on7 = x"FF" then
T_on7 <= (others => '0');
end if;
-- CH8 PWM
if T_on8 <= T_cmp8 then
triger(7) <= '1';
else
triger(7) <= '0';
end if;
if T_on8 = x"FF" then
T_on8 <= (others => '0');
end if;
end if;
end process;
-- 7 Segment display
-- Use time
-- 20000000: Tcycle = 1S = 1 Hz
process(CLK,RST_DB)
variable temp : STD_LOGIC_VECTOR (24 downto 0);
begin
if RST = '0' then
temp := (others => '0');
CLK_1 <= '0';
elsif CLK'event and CLK = '0' then
-- F = 20KHz
temp := temp 1;
if temp = '1' & x"312D00" then
temp := (others => '0');
CLK_1 <= not CLK_1;
end if;
end if;
end process;
-- BIN to BCD
process(CLK_1,RST)
begin
if RST = '0' then
D_BCD <= (others => '0');
elsif rising_edge(CLK_1) then
-- second
if D_BCD(3 downto 0) < x"9" then
min <= '0';
hour <= '0';
D_BCD(3 downto 0) <= D_BCD(3 downto 0) 1;
elsif D_BCD(3 downto 0) = x"9" then
D_BCD(3 downto 0) <= x"0";
D_BCD(7 downto 4) <= D_BCD(7 downto 4) 1;
if D_BCD(7 downto 4) = x"5" then
D_BCD(7 downto 4) <= x"0";
min <= '1';
end if;
end if;
-- minute
if D_BCD(11 downto 8) < x"9" and min = '1' then
D_BCD(11 downto 8) <= D_BCD(11 downto 8) 1;
elsif D_BCD(11 downto 8) = x"9" then
D_BCD(11 downto 8) <= x"0";
D_BCD(15 downto 12) <= D_BCD(15 downto 12) 1;
if D_BCD(15 downto 12) = x"5" then
D_BCD(15 downto 12) <= x"0";
hour <= '1';
end if;
end if;
-- hour
if D_BCD(19 downto 16) < x"3" and hour = '1' then
D_BCD(19 downto 16) <= D_BCD(19 downto 16) 1;
elsif D_BCD(19 downto 16) = x"3" then
D_BCD(19 downto 16) <= x"0";
D_BCD(23 downto 20) <= D_BCD(23 downto 20) 1;
if D_BCD(23 downto 20) = x"2" then
D_BCD(23 downto 20) <= x"0";
end if;
end if;
end if;
end process;
-- Scan
process(RST_DB,S_triger)
begin
if RST_DB = '0' then
S_scan <= "11111110";
elsif rising_edge(S_triger) then
S_scan <= S_scan(6 downto 0) & S_scan(7);
end if;
end process;
-- BCD to 7 segment
process(RST_DB,S_scan)
begin
if RST_DB = '0' then
data <= x"FF";
end if;
case S_scan is
when "11111110" =>
case D_BCD(3 downto 0) is
when x"0" => data <= x"C0";
when x"1" => data <= x"F9";
when x"2" => data <= x"A4";
when x"3" => data <= x"B0";
when x"4" => data <= x"99";
when x"5" => data <= x"92";
when x"6" => data <= x"82";
when x"7" => data <= x"F8";
when x"8" => data <= x"80";
when x"9" => data <= x"90";
when others => data <= x"FF";
end case;
when "11111101" =>
case D_BCD(7 downto 4) is
when x"0" => data <= x"C0";
when x"1" => data <= x"F9";
when x"2" => data <= x"A4";
when x"3" => data <= x"B0";
when x"4" => data <= x"99";
when x"5" => data <= x"92";
when x"6" => data <= x"82";
when x"7" => data <= x"F8";
when x"8" => data <= x"80";
when x"9" => data <= x"90";
when others => data <= x"FF";
end case;
when "11111011" =>
case D_BCD(11 downto 8)is
when x"0" => data <= x"C0";
when x"1" => data <= x"F9";
when x"2" => data <= x"A4";
when x"3" => data <= x"B0";
when x"4" => data <= x"99";
when x"5" => data <= x"92";
when x"6" => data <= x"82";
when x"7" => data <= x"F8";
when x"8" => data <= x"80";
when x"9" => data <= x"90";
when others => data <= x"FF";
end case;
when "11110111" =>
case D_BCD(15 downto 12)is
when x"0" => data <= x"C0";
when x"1" => data <= x"F9";
when x"2" => data <= x"A4";
when x"3" => data <= x"B0";
when x"4" => data <= x"99";
when x"5" => data <= x"92";
when x"6" => data <= x"82";
when x"7" => data <= x"F8";
when x"8" => data <= x"80";
when x"9" => data <= x"90";
when others => data <= x"FF";
end case;
when "11101111" =>
case D_BCD(19 downto 16)is
when x"0" => data <= x"C0";
when x"1" => data <= x"F9";
when x"2" => data <= x"A4";
when x"3" => data <= x"B0";
when x"4" => data <= x"99";
when x"5" => data <= x"92";
when x"6" => data <= x"82";
when x"7" => data <= x"F8";
when x"8" => data <= x"80";
when x"9" => data <= x"90";
when others => data <= x"FF";
end case;
when "11011111" =>
case D_BCD(23 downto 20)is
when x"0" => data <= x"C0";
when x"1" => data <= x"F9";
when x"2" => data <= x"A4";
when x"3" => data <= x"B0";
when x"4" => data <= x"99";
when x"5" => data <= x"92";
when x"6" => data <= x"82";
when x"7" => data <= x"F8";
when x"8" => data <= x"80";
when x"9" => data <= x"90";
when others => data <= x"FF";
end case;
when others => data <= x"FF";
end case;
end process;
-- Basic clock generate
process(CLK,RST_DB)
begin
if RST_DB = '0' then
DEVIDER <= (others => '0');
elsif rising_edge(CLK) then
DEVIDER <= DEVIDER 1;
end if;
end process;
T_triger <= DEVIDER(20) when CLK_SET(0) = '0' else -- fast
DEVIDER(21) when CLK_SET(1) = '0' else -- meld
DEVIDER(22); -- slow
S_triger <= DEVIDER(12);
-- Debounce
process(CLK,RST)
variable R_bounce : STD_LOGIC_VECTOR (20 downto 0) := (others => '0');
begin
-- RST debounce
if RST = '0' then
if CLK'event and CLK = '1' then
R_bounce := R_bounce 1;
end if;
else
R_bounce := (others => '0');
end if;
RST_DB <= not R_bounce(20);
end process;
-- All output
-- LED PWM output
PWM_OUT <= not triger;
-- 7 segment output
SCAN <= S_scan;
D_BUS <= data and x"7F" when (S_scan = "11101111") and (CLK_1 = '1') else
data and x"7F" when (S_scan = "11111011") and (CLK_1 = '1') else
data;
BZ <= triger(0);
end Behavioral;

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