以下是程式請各位高手教ㄧ下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clk_div_music is
generic(divisor:integer:=31);
port(
clk_in : in std_logic;
clk_out: out std_logic
);
end clk_div_music;
architecture arch of clk_div_music is
signal cnt2 : std_logic;
begin
---------- clk divider ----------
process(clk_in)
variable cnt1,divisor2 : integer range 0 to divisor;
begin
divisor2:=divisor/2;
----- up counter -----
if (clk_in'event and clk_in='1') then
if cnt1 = divisor then
cnt1 := 1;
else
cnt1 := cnt1 1;
end if;
end if;
----- clk_out register clk generator -----
if (clk_in'event and clk_in='1') then
if (( cnt1 = divisor2) or (cnt1 = divisor))then
cnt2 <= not cnt2 ;
end if;
end if;
clk_out <= cnt2 ;
end process;
end arch;
--------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity music_gene is
port(
clk : in std_logic;
clk1,clk2,clk3,clk4,clk5,clk6,clk7,clk8 : out std_logic
);
end music_gene;
architecture arch of music_gene is
component clk_div_music
generic(divisor:integer:=8);
port(
clk_in : in std_logic;
clk_out: out std_logic
);
end component;

begin
u1: clk_div_music
generic map(38226) --Do 261.6Hz
port map(clk,clk1);
u2: clk_div_music
generic map(34048) --Rai 293.7Hz
port map(clk,clk2);
u3: clk_div_music
generic map(30339) --Mi 329.6Hz
port map(clk,clk3);
u4: clk_div_music
generic map(28638) --Fa 349.1Hz
port map(clk,clk4);
u5: clk_div_music
generic map(25510) --so 392.0Hz
port map(clk,clk5);
u6: clk_div_music
generic map(22727) --La 440.0Hz
port map(clk,clk6);
u7: clk_div_music
generic map(20275) --si 493.2Hz
port map(clk,clk7);
u8: clk_div_music
generic map(19109) --Do 523.3Hz
port map(clk,clk8);

end arch;
----------------------------------------------------------------------------------------------------------------
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXstate is
port( D0,D1,D2,D3,D4,D5,D6,D7,D8:IN STD_LOGIC;
S :IN STD_LOGIC_VECTOR(3 downto 0);
Op :OUT STD_LOGIC);
end MUXstate;

architecture a of MUXstate is
begin
OP <=D0 when S="0000" ELSE
D1 when S="0001" ELSE
D2 when S="0010" ELSE
D3 when S="0011" ELSE
D4 when S="0100" ELSE
D5 when S="0101" ELSE
D6 when S="0110" ELSE
D7 when S="0111" ELSE
D8 ;
end a;
--------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY state_counter IS
PORT (clock : IN std_logic;
sel : OUT std_logic_vector(3 downto 0));
END state_counter;
ARCHITECTURE a OF state_counter IS
TYPE state IS ( S0, S1, S2, S3, S4, S5, S6, S7,S8, S9, S10, S11, S12);
SIGNAL present_state, next_state : state;
BEGIN

state_comp:PROCESS (present_state)
BEGIN
CASE present_state IS
WHEN S0 =>
sel<="0101";
next_state <= S1;
WHEN S1 =>
sel<="0011";
next_state <= S2;
WHEN S2 =>
sel<="0011";
next_state <= S3;
WHEN S3 =>
sel<="0100";
next_state <= S4;
WHEN S4 =>
sel<="0010";
next_state <= S5;
WHEN S5 =>
sel<="0010";
next_state <= S6;
WHEN S6 =>
sel<="0001";
next_state <= S7;
WHEN S7 =>
sel<="0010";
next_state <= S8;
WHEN S8 =>
sel<="0011";
next_state <= S9;
WHEN S9 =>
sel<="0100";
next_state <= S10;
WHEN S10 =>
sel<="0101";
next_state <= S11;
WHEN S11 =>
sel<="0101";
next_state <= S12;
WHEN S12 =>
sel<="0101";
next_state <= S0;
END CASE;
END PROCESS state_comp;
state_clocking :PROCESS (clock)
BEGIN
IF clock'event and clock='1' THEN
present_state <= next_state ;
END IF ;
END PROCESS state_clocking;
END a;

您好
你所參考的那本書,第3-76頁
圖3-47那個圖說明的很清楚