有關FPGA的LCG_希望大家能幫我一下~

發表時間：2007-06-05 10:18:31

IP:140.128.xxx.xxx 訂閱

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MOVING_PIXIE is
Port ( CLK : in std_logic;
RESET : in std_logic;
LGM_ENABLE : out std_logic;
LGM_RW : out std_logic;
LGM_DI : out std_logic;
LGM_CS1 : out std_logic;
LGM_CS2 : out std_logic;
LGM_RST : out std_logic;
LGM_DATA : out std_logic_vector(7 downto 0));
end MOVING_PIXIE;
architecture Behavioral of MOVING_PIXIE is
signal LGM_CLK : std_logic;
signal CLEAR : std_logic;
signal DIVIDER : std_logic_vector(15 downto 0);
signal ENABLE : std_logic_vector(1 downto 0);
signal LGM_SEL : std_logic_vector(1 downto 0);
signal DELAY : std_logic_vector(15 downto 0);
signal X_PAGE : std_logic_vector(2 downto 0);

type ROM is array(0 to 63) of std_logic_vector(7 downto 0);
constant UPPER_PATTERN : ROM :=
(x"00",x"E0",x"F8",x"FC",x"FE",x"FE",x"FF",x"FF",
x"FF",x"FF",x"FF",x"FE",x"FE",x"FC",x"F8",x"E0",
x"00",x"E0",x"F8",x"FC",x"FE",x"FE",x"FF",x"FF",
x"7F",x"7F",x"7F",x"7E",x"3E",x"3C",x"38",x"20",
x"00",x"E0",x"F8",x"FC",x"FE",x"FE",x"FF",x"FF",
x"7F",x"7F",x"3F",x"3E",x"3E",x"1C",x"18",x"10",
x"00",x"E0",x"F8",x"FC",x"FE",x"FE",x"FF",x"FF",
x"7F",x"3F",x"3F",x"1E",x"1E",x"0C",x"08",x"00");

constant LOWER_PATTERN : ROM :=
(x"00",x"03",x"0F",x"1F",x"3F",x"3F",x"7F",x"7F",
x"7F",x"7F",x"7F",x"3F",x"3F",x"1F",x"0F",x"03",
x"00",x"03",x"0F",x"1F",x"3F",x"3F",x"7F",x"7F",
x"7F",x"7F",x"7F",x"3F",x"3E",x"1E",x"0E",x"02",
x"00",x"03",x"0F",x"1F",x"3F",x"3F",x"7F",x"7F",
x"7F",x"7F",x"7E",x"3E",x"3E",x"1C",x"0C",x"04",
x"00",x"03",x"0F",x"1F",x"3F",x"3F",x"7F",x"7F",
x"7F",x"7E",x"7E",x"3C",x"3C",x"18",x"08",x"00");

begin
--=========================
--= Time Base Generator =
--=========================
process(CLK,RESET)

begin
if RESET = '0' then
DIVIDER<= (others => '0');
elsif CLK'event and CLK ='1' then
DIVIDER<= DIVIDER 1;
end if;
end process;
LGM_CLK <= DIVIDER(8);

--==============================
--= Initial And Write LGM Data =
--==============================

process(LGM_CLK,RESET)
variable STATE : integer range 0 to 5;
variable COUNTER : integer range 0 to 16;
variable Y_INDEX : integer range 0 to 127;
variable PAGE : integer range 0 to 127;
variable DISPLAY_INDEX : integer range 0 to 80;
begin
if RESET = '0' then
DELAY <= (others => '0');
ENABLE <= "00";
CLEAR <= '1';
X_PAGE <= o"0";
LGM_SEL <= "11";
LGM_RST <= '0';
LGM_RW <= '0';
LGM_DI <= '0';
STATE := 0;
Y_INDEX := 0;
PAGE := 0;
COUNTER := 0;
DISPLAY_INDEX := 0;
elsif LGM_CLK'event and LGM_CLK ='1' then
if ENABLE < "10" then
ENABLE <= ENABLE 1;
DELAY(1) <= '1';
elsif DELAY /= x"0000" then
DELAY <= DELAY - 1;
elsif STATE = 0 then
STATE := 1;
LGM_RST <= '1';
LGM_DATA <= x"3F";
ENABLE <= "00";
elsif STATE = 1 then
STATE := 2;
LGM_DATA<= x"C0";
ENABLE <= "00";
elsif STATE = 2 then
STATE := 3;
LGM_DI <= '0';
LGM_DATA<= "10111" & X_PAGE;
ENABLE <= "00";
elsif STATE = 3 then
STATE := 4;
LGM_DI <= '0';
LGM_DATA<= "01"& conv_std_logic_vector(Y_INDEX,6);
ENABLE <= "00";
elsif STATE = 4 then
if CLEAR = '1' then
if Y_INDEX < 64 then
LGM_DI <= '1';
Y_INDEX := Y_INDEX 1;
LGM_DATA<= (others=>'0');
ENABLE <= "00";
elsif X_PAGE < o"7" then
STATE := 2;
X_PAGE <= X_PAGE 1;
Y_INDEX:= 0;
else
STATE := 2;
Y_INDEX := 0;
X_PAGE <= o"3";
CLEAR <= '0';
end if;
else
STATE := 5;
if Y_INDEX < 64 then
LGM_SEL <= "10";
else
LGM_SEL <= "01";
end if;
end if;
elsif STATE = 5 then -- LGM_DIsplay LGM_DATA
STATE := 2;
if COUNTER < 16 then
LGM_DI <= '1';
if X_PAGE = o"3" then
X_PAGE <= o"4";
LGM_DATA<= UPPER_PATTERN(DISPLAY_INDEX);
else
X_PAGE <= o"3";
LGM_DATA <= LOWER_PATTERN(DISPLAY_INDEX);
Y_INDEX := Y_INDEX 1;
DISPLAY_INDEX := DISPLAY_INDEX 1;
COUNTER := COUNTER 1;
end if;
ENABLE <= "00";
else
COUNTER := 0;
PAGE := PAGE 1;
Y_INDEX := PAGE;
DELAY(15) <= '1';
end if;
end if;
end if;
end process;
LGM_ENABLE<= ENABLE(0);
LGM_CS1 <= LGM_SEL(0);
LGM_CS2 <= LGM_SEL(1);

end Behavioral;

能幫我看一下這是那邊出了錯誤~
DBOG是沒有錯誤的~我覺得可能是邏輯想法有錯吧~~

這個是做~在LCG上有隻小精靈在跑~~
但是我從第一個LCG切換到第二個LCG時~會有殘影~之後就一直有殘影
也看不出我錯在哪~~
希望有經驗的大大能幫我一下~謝謝
所用程式~Xilinx ISE 8.1i
所用接腳
NET "CLK" LOC = "p80" ;
NET "LGM_CS1" LOC = "p205" ;
NET "LGM_CS2" LOC = "p204" ;
NET "LGM_DATA<0>" LOC = "p111" ;
NET "LGM_DATA<1>" LOC = "p112" ;
NET "LGM_DATA<2>" LOC = "p113" ;
NET "LGM_DATA<3>" LOC = "p114" ;
NET "LGM_DATA<4>" LOC = "p115" ;
NET "LGM_DATA<5>" LOC = "p119" ;
NET "LGM_DATA<6>" LOC = "p120" ;
NET "LGM_DATA<7>" LOC = "p121" ;
NET "LGM_DI" LOC = "p108" ;
NET "LGM_ENABLE" LOC = "p110" ;
NET "LGM_RST" LOC = "p206" ;
NET "LGM_RW" LOC = "p109" ;
NET "RESET" LOC = "p180" ;