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利用VHDL來顯示在點矩陣,並加上PWM控制

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asd091115
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註冊:2013-09-05

發送簡訊給我
#1 引用回覆 回覆 發表時間:2013-09-05 20:29:44 IP:59.124.xxx.xxx 訂閱
如標題

因為本人只是個學生~

目前只會利用VHDL來顯示在點矩陣上

但是我想要利用PWM控制顏色~

請求支援QQ

----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--主程式
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--*****************************************************************************
-- Date : 102/08/16
-- Auther :
-- School : Daan_Electronics
-- FPGA : Cyclone III (EP3C10E144C8N)
-- Lab : dot_matrix with keyboard (keyboard_1) and clock(setting/1224)
-- LEs : 706/10320 (7%)
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--*****************************************************************************
entity dot_matrix_5 is
generic(fmax : integer := 25000000);
port(
-- input signals
clk : in std_logic; -- clk = 25MHz,Pin=91
kb_col : in std_logic_vector( 3 downto 0); -- column inputs
sw1 : in std_logic; -- Hightlight (Low-actived)
sw2 : in std_logic; -- Don't care (Low-actived)
sw3 : in std_logic; -- Clock Setting (Low-actived)
-- output signals
kb_row : out std_logic_vector( 3 downto 0); -- scan keyboard
seg7_out : out std_logic_vector( 7 downto 0);
scan_seg : out std_logic_vector( 3 downto 0);
scan_16 : out std_logic_vector(15 downto 0);
red_col : out std_logic_vector(15 downto 0);
gre_col : out std_logic_vector(15 downto 0)
);
end dot_matrix_5;
--*****************************************************************************
architecture beh of dot_matrix_5 is
signal rst : std_logic;
signal clk_1Hz : std_logic;
signal clk_1p : std_logic;
signal row_cnt : integer range 0 to 7;
signal scan : std_logic_vector(3 downto 0);
-- keyboard
signal kb_code : std_logic_vector(3 downto 0);
signal kb_done_p : std_logic;
-- flag
signal flag_color : std_logic_vector(1 downto 0);
signal flag_sys : std_logic;
-- sw
signal sample : std_logic;
signal dly : std_logic;
signal diff_np : std_logic_vector(2 downto 0);
signal diff_pp : std_logic_vector(2 downto 0);
signal key_in : std_logic_vector(2 downto 0);
signal flt : std_logic_vector(2 downto 0);
-- diff
signal h_light : std_logic;
signal h_light_p : std_logic;
signal color_p : std_logic;
signal sys_p : std_logic;
-- dot matrix
type ROM is array(0 to 15,0 to 7) of std_logic_vector(7 downto 0);

constant Font_ROM : ROM -- 8X8 Font
:= ((x"3C",x"7E",x"66",x"66",x"66",x"66",x"7E",x"3C"), -- 0
(x"1C",x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C"), -- 1
(x"3C",x"6E",x"0E",x"0E",x"1C",x"38",x"70",x"7E"), -- 2
(x"3C",x"7E",x"0E",x"1C",x"0E",x"06",x"6E",x"3C"), -- 3
(x"0C",x"1C",x"3C",x"6C",x"6C",x"7E",x"0C",x"0C"), -- 4
(x"7E",x"60",x"60",x"7E",x"76",x"06",x"6E",x"3C"), -- 5
(x"3C",x"66",x"60",x"7C",x"76",x"66",x"76",x"3C"), -- 6
(x"7E",x"0E",x"0C",x"1C",x"18",x"18",x"18",x"18"), -- 7
(x"3C",x"66",x"7E",x"3C",x"7E",x"66",x"7E",x"3C"), -- 8
(x"3C",x"7E",x"66",x"7E",x"3E",x"06",x"6E",x"3C"), -- 9
(x"18",x"3C",x"66",x"66",x"7E",x"66",x"66",x"66"), -- A
(x"7C",x"66",x"66",x"7C",x"66",x"66",x"66",x"7C"), -- B
(x"3E",x"E7",x"E3",x"C0",x"C0",x"E3",x"E7",x"7E"), -- C
(x"7C",x"6E",x"66",x"62",x"62",x"66",x"6E",x"7C"), -- D
(x"7E",x"60",x"60",x"7E",x"60",x"60",x"60",x"7E"), -- E
(x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"60") -- F
);
-- RAM1 (row) (col)
type RAM1 is array (0 to 7) of std_logic_vector(7 downto 0);
signal LU_RAM1 : RAM1;
signal LD_RAM1 : RAM1;
signal RU_RAM1 : RAM1;
signal RD_RAM1 : RAM1;
-- RAM2 (row) (color)
type RAM2 is array (0 to 7) of std_logic_vector(2 downto 0);
signal LU_RAM2 : RAM2 := ("010","010","010","010","010","010","010","010");
signal LD_RAM2 : RAM2 := ("001","001","001","001","001","001","001","001");
signal RU_RAM2 : RAM2 := ("100","100","100","100","100","100","100","100");
signal RD_RAM2 : RAM2 := ("010","010","010","010","010","010","010","010");
-------------------------------------------------------------------------------
component clk_elect
port(
-- input signals
clk : in std_logic; -- clk = 25MHz,Pin = 91
scan : in std_logic_vector(1 downto 0);
flag_sys : in std_logic;
kb_code : in std_logic_vector(3 downto 0);
kb_done_p: in std_logic;
-- output signals
seg_out : out std_logic_vector(7 downto 0);-- High actived
scan_seg : out std_logic_vector(3 downto 0) -- High actived
);
end component;

component keyboard_1
port(
-- input signals
clk : in std_logic;--clk = 25MHz,Pin=91
rst : in std_logic;
col : in std_logic_vector(3 downto 0); -- column inputs
-- output signals
row : out std_logic_vector(3 downto 0); -- scan keyboard
key_code : out std_logic_vector(3 downto 0);
done_pulse : out std_logic
);
end component;
--*****************************************************************************
begin
-- Components Realization
u1 : clk_elect port map(clk,scan(1 downto 0),flag_sys,kb_code,kb_done_p,seg7_out,scan_seg);
u2 : keyboard_1 port map(clk,rst,kb_col,kb_row,kb_code,kb_done_p);
-- System connections
row_cnt <= conv_integer(scan(2 downto 0));
key_in <= sw3 & sw2 & sw1;
h_light_p <= diff_np(0);
color_p <= diff_np(1);
sys_p <= diff_np(2);
--*****************************************************************************
-- 26bits free counter(L->H or H->L)
x1 : block
signal cnt1,cnt2,cnt3 : std_logic_vector(25 downto 0);-- totally 26 bits
begin
process(clk)
begin
if(clk'event and clk = '1')then -- Postive-Edge Trigger
-- power on : auto reset signal(Low actived)
if(cnt1 < fmax-1)then
cnt1 <= cnt1 1;
rst <= '0';
else
rst <= '1';
end if;
-- 1Hz & 1Hz_Pulse
if(cnt2 < fmax/2 - 1)then
cnt2 <= cnt2 1;
clk_1Hz <= '0';
clk_1p <= '0';
elsif(cnt2 < fmax - 1)then
cnt2 <= cnt2 1;
clk_1Hz <= '1';
clk_1p <= '0';
else
cnt2 <= (others => '0');
clk_1Hz <= '1';
clk_1p <= '1';
end if;
-- sample & scan
cnt3 <= cnt3 1;
dly <= cnt3(13);
end if;
end process;
scan <= cnt3(16 downto 13); -- 25MHz / 2^14 = 1525.88 Hz
sample <= (not dly) and cnt3(13); -- 25MHz / 2^14 = 1525.88 Hz
end block x1;
--*****************************************************************************
-- Switches debouncing
x2 : block
signal q0,q1 : std_logic_vector(2 downto 0);-- Length = SW numbers
begin
process(clk,rst) --diff
begin
if(rst = '0')then
flt <= (others => '0');
elsif(clk'event and clk = '1')then -- Postive-Edge Trigger
if(sample = '1')then
q1 <= q0;
q0 <= key_in; -- input signals write here
--flt <= ((q0 and q1) or flt) and(q0 or q1); -- RS-FF(output)
flt <= (q0 and q1) or ((q0 or q1) and flt); -- RS-FF(output)
end if;
end if;
end process;
end block x2;
-----------------------------------------------------------------------
-- Differential signals
x3 : block
signal q0,q1 : std_logic_vector(2 downto 0);-- Length = SW numbers
begin
process(clk,rst)
begin
if(rst = '0')then
q1 <= (others => '0');
q0 <= (others => '0');
elsif (clk'event and clk = '1')then -- Postive-Edge Trigger
q1 <= q0;
q0 <= flt; -- differential input write here
end if;
end process;
diff_np <= q1 and (not q0); -- catch negative edge
diff_pp <=(not q1) and q0; -- catch positive edge
end block x3;
--*****************************************************************************
-- Character's Font Shift
process(clk,rst)
begin
if(rst = '0')then
LU_RAM1 <= (x"3C",x"7E",x"66",x"66",x"66",x"66",x"7E",x"3C"); -- 0
RU_RAM1 <= (x"3C",x"7E",x"66",x"66",x"66",x"66",x"7E",x"3C"); -- 0
LD_RAM1 <= (x"3C",x"7E",x"66",x"66",x"66",x"66",x"7E",x"3C"); -- 0
RD_RAM1 <= (x"3C",x"7E",x"66",x"66",x"66",x"66",x"7E",x"3C"); -- 0
elsif(clk'event and clk = '1')then -- Positive-Edge Trigger
if(kb_done_p = '1' and flag_sys = '0')then
LU_RAM1 <= RU_RAM1;
RU_RAM1 <= LD_RAM1;
LD_RAM1 <= RD_RAM1;
for i in 0 to 7 loop -- New Key_in Data Font
RD_RAM1(i) <= Font_ROM(conv_integer(kb_code),i);
end loop;
end if;
end if;
end process;
--*****************************************************************************
-- Highlight
process(clk,rst)
begin
if(rst = '0')then
h_light <= '0';
elsif(clk'event and clk = '1')then
if(h_light_p = '1')then
h_light <= not h_light;
end if;
end if;
end process;
--*****************************************************************************
-- Dot matrix column Signals
process(clk,rst)
begin
if(rst = '0')then
gre_col <= (others => '0');
red_col <= (others => '0');
elsif(clk'event and clk = '1')then
if(h_light = '0')then -- Upper RAMs
if(scan(3) = '0')then
for i in 0 to 7 loop
-- Left Upper RAM
if(LU_RAM2(i) = 0)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= (others => '0');
elsif(LU_RAM2(i) = 1)then
gre_col(15 downto 8) <= LU_RAM1(row_cnt);
red_col(15 downto 8) <= (others => '0');
elsif(LU_RAM2(i) = 2)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= LU_RAM1(row_cnt);
elsif(LU_RAM2(i) = 4)then
gre_col(15 downto 8) <= LU_RAM1(row_cnt);
red_col(15 downto 8) <= LU_RAM1(row_cnt);
end if;
-- Right Upper RAM
if(RU_RAM2(i) = 0)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= (others => '0');
elsif(RU_RAM2(i) = 1)then
gre_col(7 downto 0) <= RU_RAM1(row_cnt);
red_col(7 downto 0) <= (others => '0');
elsif(RU_RAM2(i) = 2)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= RU_RAM1(row_cnt);
elsif(RU_RAM2(i) = 4)then
gre_col(7 downto 0) <= RU_RAM1(row_cnt);
red_col(7 downto 0) <= RU_RAM1(row_cnt);
end if;
end loop;
else -- Down RAMs
for i in 0 to 7 loop
-- Left Down RAM
if(LD_RAM2(i) = 0)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= (others => '0');
elsif(LD_RAM2(i) = 1)then
gre_col(15 downto 8) <= LD_RAM1(row_cnt);
red_col(15 downto 8) <= (others => '0');
elsif(LD_RAM2(i) = 2)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= LD_RAM1(row_cnt);
elsif(LD_RAM2(i) = 4)then
gre_col(15 downto 8) <= LD_RAM1(row_cnt);
red_col(15 downto 8) <= LD_RAM1(row_cnt);
end if;
-- Right Down RAM
if(RD_RAM2(i) = 0)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= (others => '0');
elsif(RD_RAM2(i) = 1)then
gre_col(7 downto 0) <= RD_RAM1(row_cnt);
red_col(7 downto 0) <= (others => '0');
elsif(RD_RAM2(i) = 2)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= RD_RAM1(row_cnt);
elsif(RD_RAM2(i) = 4)then
gre_col(7 downto 0) <= RD_RAM1(row_cnt);
red_col(7 downto 0) <= RD_RAM1(row_cnt);
end if;
end loop;
end if;
else -- h_light = '1'
if(scan(3) = '0')then -- Upper RAMs
for i in 0 to 7 loop
-- Left Upper RAM
if(LU_RAM2(i) = 0)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= (others => '0');
elsif(LU_RAM2(i) = 1)then
gre_col(15 downto 8) <= not(LU_RAM1(row_cnt));
red_col(15 downto 8) <= (others => '0');
elsif(LU_RAM2(i) = 2)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= not(LU_RAM1(row_cnt));
elsif(LU_RAM2(i) = 4)then
gre_col(15 downto 8) <= not(LU_RAM1(row_cnt));
red_col(15 downto 8) <= not(LU_RAM1(row_cnt));
end if;
-- Right Upper RAM
if(RU_RAM2(i) = 0)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= (others => '0');
elsif(RU_RAM2(i) = 1)then
gre_col(7 downto 0) <= not(RU_RAM1(row_cnt));
red_col(7 downto 0) <= (others => '0');
elsif(RU_RAM2(i) = 2)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= not(RU_RAM1(row_cnt));
elsif(RU_RAM2(i) = 4)then
gre_col(7 downto 0) <= not(RU_RAM1(row_cnt));
red_col(7 downto 0) <= not(RU_RAM1(row_cnt));
end if;
end loop;
else -- Down RAMs
for i in 0 to 7 loop
-- Left Down RAM
if(LD_RAM2(i) = 0)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= (others => '0');
elsif(LD_RAM2(i) = 1)then
gre_col(15 downto 8) <= not(LD_RAM1(row_cnt));
red_col(15 downto 8) <= (others => '0');
elsif(LD_RAM2(i) = 2)then
gre_col(15 downto 8) <= (others => '0');
red_col(15 downto 8) <= not(LD_RAM1(row_cnt));
elsif(LD_RAM2(i) = 4)then
gre_col(15 downto 8) <= not(LD_RAM1(row_cnt));
red_col(15 downto 8) <= not(LD_RAM1(row_cnt));
end if;
-- Right Down RAM
if(RD_RAM2(i) = 0)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= (others => '0');
elsif(RD_RAM2(i) = 1)then
gre_col(7 downto 0) <= not(RD_RAM1(row_cnt));
red_col(7 downto 0) <= (others => '0');
elsif(RD_RAM2(i) = 2)then
gre_col(7 downto 0) <= (others => '0');
red_col(7 downto 0) <= not(RD_RAM1(row_cnt));
elsif(RD_RAM2(i) = 4)then
gre_col(7 downto 0) <= not(RD_RAM1(row_cnt));
red_col(7 downto 0) <= not(RD_RAM1(row_cnt));
end if;
end loop;
end if;
end if;
end if;
end process;
--*****************************************************************************
-- Setting mode
x4 : block
signal flag_mode : std_logic;
signal cnt_mode : std_logic_vector(1 downto 0);
begin
process(clk,rst) --set start
begin
if(rst = '0')then
flag_sys <= '0';
flag_mode <= '0';
cnt_mode <= (others => '0');
elsif(clk'event and clk = '1')then -- Postive-Edge Trigger
-- system setting
if(sys_p = '1' and flag_sys = '0')then
flag_mode <= not flag_mode;
end if;

if(clk_1p= '1' and flag_mode = '1' and sw3 = '0')then -- SW3 pressed 3 Sec.
cnt_mode <= cnt_mode 1;
end if;

if(cnt_mode = 3)then
flag_sys <= '1';
cnt_mode <= (others => '0');
end if;

if(sys_p = '1' and flag_sys = '1')then
flag_sys <= '0';
flag_mode <= '0';
cnt_mode <= (others => '0');
end if;
end if;
end process;
end block x4;
--*****************************************************************************
-- Decoder (4 to 16),Scan Freq.= 25MHz / 2^14 = 1525.88 Hz
with scan select
scan_16 <= "0000000000000001" when "0000", -- row 0
"0000000000000010" when "0001", -- row 1
"0000000000000100" when "0010", -- row 2
"0000000000001000" when "0011", -- row 3
"0000000000010000" when "0100", -- row 4
"0000000000100000" when "0101", -- row 5
"0000000001000000" when "0110", -- row 6
"0000000010000000" when "0111", -- row 7
"0000000100000000" when "1000", -- row 8
"0000001000000000" when "1001", -- row 9
"0000010000000000" when "1010", -- row10
"0000100000000000" when "1011", -- row11
"0001000000000000" when "1100", -- row12
"0010000000000000" when "1101", -- row13
"0100000000000000" when "1110", -- row14
"1000000000000000" when others; -- row15
--*****************************************************************************
end beh;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- Component
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- Keyboard
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--*****************************************************************************
--Date : 102/07/29-102/07/30
--Auther : Lee Hao Wei
--School : Daan_Electronics
--FPGA : Cyclone III (EP3C10E144C8N)
--Lab : 4x4 Keybord Scan with 8 digits 7-Segments Display (4 digits * 2)
--LEs : 55/10320(<1%)
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--*****************************************************************************
entity keyboard_1 is
generic(fmax : integer := 25000000);
port(
-- input signals
clk : in std_logic;--clk = 25MHz,Pin=91
rst : in std_logic;
col : in std_logic_vector(3 downto 0); -- column inputs
-- output signals
row : out std_logic_vector(3 downto 0); -- scan keyboard
key_code : out std_logic_vector(3 downto 0);
done_pulse : out std_logic
);
end keyboard_1;
--*****************************************************************************
architecture beh of keyboard_1 is
signal sample : std_logic; -- sampling frequency
signal key_in : std_logic; -- all coi_in
signal flt : std_logic;
signal diff_pp : std_logic;
signal diff_np : std_logic;
signal kb_cnt : std_logic_vector(1 downto 0); -- for keyboard scanning
signal temp_col : std_logic_vector(3 downto 0);
signal latch_dly : std_logic_vector(3 downto 0);
signal key_press : std_logic;
--*****************************************************************************
begin
-- system connections
-- input
key_in <= col(3) or col(2) or col(1) or col(0);
-- output
done_pulse <= latch_dly(2);
--*****************************************************************************
-- 20bits free counter(L->H or H->L) 25MHz/1Hz/1Hz_pulse
x1 : block
signal cnt1 : std_logic_vector(19 downto 0); -- totally 20 bits
signal cnt2 : std_logic_vector(19 downto 0);
signal dly : std_logic;
begin
process(clk)
begin
if(clk'event and clk = '1')then -- Postive-Edge Trigger
cnt1 <= cnt1 1;
dly <= cnt1(13);
end if;
end process;

process(clk)
begin
if(clk'event and clk = '1')then -- Postive-Edge Trigger
if(key_press = '0')then -- key_press = '1' : stop row scanning
cnt2 <= cnt2 1;
end if;
end if;
end process;
sample <= (not dly) and cnt1(13);-- 25MHz / 2^14 = 1525.88 Hz
-- sample >= 8 * kb_cnt
kb_cnt <= cnt2(17 downto 16); -- 25MHz / 2^17 = 762.94 Hz
end block x1;
--*****************************************************************************
-- Switches debouncing
x2 : block
signal q0,q1 : std_logic;-- Length = SW numbers
begin
process(clk,rst)
begin
if(rst = '0')then
flt <= '0';
elsif(clk'event and clk = '1')then -- Postive-Edge Trigger
if(sample = '1')then
q1 <= q0;
q0 <= key_in; -- input signals write here
--flt <= ((q0 and q1) or flt) and(q0 or q1); -- RS-FF(output)
flt <= (q0 and q1) or ((q0 or q1) and flt); -- RS-FF(output)
end if;
end if;
end process;
end block x2;
-----------------------------------------------------------------------
-- Differential signal
x3 : block
signal q0,q1 : std_logic;-- Length = SW numbers
begin
process(clk,rst)
begin
if(rst = '0')then
q1 <= '0';
q0 <= '0';
elsif (clk'event and clk = '1')then -- Postive-Edge Trigger
q1 <= q0;
q0 <= flt; -- differential input write here
end if;
end process;
diff_np <= q1 and (not q0); -- catch negative edge
diff_pp <=(not q1) and q0; -- catch positive edge
end block x3;
--*****************************************************************************
-- Generating key_press signal and col_in value latch
process(clk,rst)
begin
if(rst = '0')then
key_press <= '0';
elsif(clk'event and clk = '0')then -- Negative-Edge Trigger
if(diff_pp = '1')then
key_press <= '1'; -- kb_cnt : stop up-counting or stop kb row_scanning(Line-63)
temp_col <= col; -- col_in value latch
elsif(diff_np = '1')then
key_press <= '0';
temp_col <= (others => '0');
end if;
end if;
end process;
--*****************************************************************************
-- Done_pulse delay
process(clk)
begin
if(clk'event and clk = '1')then -- Postive-Edge Trigger
latch_dly <= latch_dly(2 downto 0) & diff_pp;
end if;
end process;
--*****************************************************************************
-- Key_code decision
process(clk,rst)
begin
if(clk'event and clk = '0')then -- Negative-Edge Trigger
if(latch_dly(0) = '1')then
case kb_cnt is
when "00" =>
if(temp_col(0) = '1')then
key_code <= "0000";
elsif(temp_col(1) = '1')then
key_code <= "0001";
elsif(temp_col(2) = '1')then
key_code <= "0010";
elsif(temp_col(3) = '1')then
key_code <= "0011";
end if;
when "01" =>
if(temp_col(0) = '1')then
key_code <= "0100";
elsif(temp_col(1) = '1')then
key_code <= "0101";
elsif(temp_col(2) = '1')then
key_code <= "0110";
elsif(temp_col(3) = '1')then
key_code <= "0111";
end if;
when "10" =>
if(temp_col(0) = '1')then
key_code <= "1000";
elsif(temp_col(1) = '1')then
key_code <= "1001";
elsif(temp_col(2) = '1')then
key_code <= "1010";
elsif(temp_col(3) = '1')then
key_code <= "1011";
end if;
when others =>
if(temp_col(0) = '1')then
key_code <= "1100";
elsif(temp_col(1) = '1')then
key_code <= "1101";
elsif(temp_col(2) = '1')then
key_code <= "1110";
elsif(temp_col(3) = '1')then
key_code <= "1111";
end if;
end case;
end if;
end if;
end process;
--*****************************************************************************
-- Row scanning decoder
with kb_cnt select
row <= "0001" when "00", -- row0 => |3|2|1|0|
"0010" when "01", -- row1 => |7|6|5|4|
"0100" when "10", -- row2 => |B|A|9|8|
"1000" when others; -- row3 => |F|E|D|C|
--*****************************************************************************
end beh;

----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--clk_elect
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--*****************************************************************************
--Date : 102/7/20-21
--Auther : Lee Hao Wei
--School : Daan_Electronics
--FPGA : Cyclone III (EP3C10E144C8N)
--Lab : 7-Segments Multiple Scan with clock(Can set)
--LEs : 507/10320(5%)
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--*****************************************************************************
entity clk_elect is
generic(fmax : integer := 25000000);
port(
-- input signals
clk : in std_logic; -- clk = 25MHz,Pin = 91
scan : in std_logic_vector(1 downto 0);
flag_sys : in std_logic;
kb_code : in std_logic_vector(3 downto 0);
kb_done_p: in std_logic;
-- output signals
seg_out : out std_logic_vector(7 downto 0);-- High actived
scan_seg : out std_logic_vector(3 downto 0) -- High actived
);
end clk_elect;
--*****************************************************************************
architecture beh of clk_elect is
signal clr : std_logic;
signal clk_1 : std_logic; -- 1Hz
signal clk_1p : std_logic; -- second pulse(T = 1 Sec.)
--Register
signal hour1 : std_logic_vector(3 downto 0);-- BCD Code Register
signal hour0 : std_logic_vector(3 downto 0);-- BCD Code Register
signal min1 : std_logic_vector(3 downto 0);-- BCD Code Register
signal min0 : std_logic_vector(3 downto 0);-- BCD Code Register
signal sec1 : std_logic_vector(3 downto 0);-- BCD Code Register
signal sec0 : std_logic_vector(3 downto 0);-- BCD Code Register
signal temp1 : std_logic_vector(3 downto 0);-- BCD Code Register
signal temp2 : std_logic_vector(7 downto 0);-- 7 seg Register
--others
signal cnt_shift : std_logic_vector(1 downto 0);
signal ampm : std_logic;
signal flag_1224 : std_logic;
--*****************************************************************************
begin
-- system connections
-- input
-- output
--*****************************************************************************
-- 26bits free counter(L->H or H->L) 25MHz/1Hz/1Hz_pulse
x1 : block
signal cnt1,cnt2 : std_logic_vector(25 downto 0);-- totally 26 bits
signal cnt3 : std_logic_vector(23 downto 0);
begin
process(clk)
begin
if(clk'event and clk = '1')then -- Postive-Edge Trigger
if(cnt1 < fmax/2 - 1)then
cnt1 <= cnt1 1;
clk_1 <= '0';
clk_1p <= '0';
elsif(cnt1 < fmax - 1)then
cnt1 <= cnt1 1;
clk_1 <= '1';
clk_1p <= '0';
else
cnt1 <= (others => '0');
clk_1p <= '1';
end if;
-- power on : auto reset signal
if(cnt2 < fmax-1)then
cnt2 <= cnt2 1;
clr <= '0';
else
clr <= '1';
end if;
end if;
end process;
end block x1;
--*****************************************************************************
-- Timer counting
process(clk,clr)
begin
if(clr = '0')then--clear/12:00:00
sec1 <= (others => '0');--"0000"
sec0 <= (others => '0');--"0000"
min1 <= (others => '0');--"0000"
min0 <= (others => '0');--"0000"
hour1 <= "0001";--1
hour0 <= "0010";--2
cnt_shift <= (others => '0');
ampm <= '0';
flag_1224 <= '0';
elsif(clk'event and clk = '0')then -- Negative-Edge Trigger
if(clk_1p = '1' and flag_sys = '0')then--計數十分秒
if (sec0 < 9)then -- sec digits
sec0 <= sec0 1;
else
sec0 <= (others => '0');
if(sec1 < 5)then
sec1 <= sec1 1; -- sec tenth
else
sec1 <= (others => '0');
if(min0 < 9)then -- min
min0 <= min0 1;
else
min0 <= (others => '0');
if(min1 < 5)then
min1 <= min1 1;
else
min1 <= (others => '0');
if(ampm = '0')then -- 12hr
if(hour1 < 1)then
if(hour0 < 9)then
hour0 <= hour0 1;
else
hour0 <= (others=> '0');
hour1 <= hour1 1;
end if;
else
if(hour0 = 0)then
hour0 <= hour0 1;
elsif(hour0 = 1)then
hour0 <= hour0 1;
else
hour0 <= "0001";
hour1 <= (others => '0');
flag_1224 <= not flag_1224;
end if;
end if;
else -- 24hr
if(hour1 < 2)then
if(hour0 < 9)then
hour0 <= hour0 1;
else
hour0 <= (others=> '0');
hour1 <= hour1 1;
end if;
else
if(hour0 < 3)then
hour0 <= hour0 1;
else
hour0 <= (others => '0');
hour1 <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end if;
end if;
elsif(flag_sys = '1' and kb_done_p = '1')then
if(kb_code < 10)then
if(ampm = '0')then
if(cnt_shift = 0)then
min0 <= kb_code;
elsif(cnt_shift = 1)then
if(kb_code < 6)then
min1 <= kb_code;
end if;
elsif(cnt_shift = 2)then
if(hour1 = 0)then
hour0 <= kb_code;
else
if(kb_code < 3)then
hour0 <= kb_code;
end if;
end if;
else
if(kb_code = 1)then
hour1 <= kb_code;
if(hour0 > 2)then
hour0 <= "0010";
end if;
elsif(kb_code = 0)then
hour1 <= kb_code;
end if;
end if;
else
if(cnt_shift = 0)then
min0 <= kb_code;
elsif(cnt_shift = 1)then
if(kb_code < 6)then
min1 <= kb_code;
end if;
elsif(cnt_shift = 2)then
if(hour1 < 2)then
hour0 <= kb_code;
else
if(kb_code < 4)then
hour0 <= kb_code;
end if;
end if;
else
if(kb_code = 2)then
if(hour0 > 3)then
hour0 <= "0011";
end if;
hour1 <= kb_code;
else
hour1 <= kb_code;
end if;
end if;
end if;
elsif(kb_code = 12)then
cnt_shift <= cnt_shift 1;
elsif(kb_code = 13)then
cnt_shift <= cnt_shift - 1;
elsif(kb_code = 15)then
ampm <= not ampm;
if(ampm = '0')then -- 12 -> 24
if(flag_1224 = '1')then
if(hour1 = 0 and hour0 < 8 )then
hour1 <= hour1 1;
hour0 <= hour0 2;
elsif(hour1 = 0 and hour0 > 7)then
hour1 <= "0010";
hour0 <= hour0 - 8;
elsif(hour1 = 1 and hour0 = 2)then
hour1 <= (others => '0');
hour0 <= (others => '0');
else
hour1 <= hour1 1;
hour0 <= hour0 2;
end if;
end if;
else -- 24 -> 12
if(hour1 = 2 and hour0 > 1)then
hour1 <= hour1 - 1;
hour0 <= hour0 - 2;
flag_1224 <= '1';
elsif(hour1 = 2 and hour0 < 2)then
hour1 <= (others => '0');
hour0 <= hour0 8;
flag_1224 <= '1';
elsif(hour1 = 1 and hour0 > 2)then
hour1 <= hour1 - 1;
hour0 <= hour0 - 2;
flag_1224 <= '1';
elsif(hour1 = 0 and hour1 = 0)then
hour1 <= "0001";
hour0 <= "0010";
flag_1224 <= '0';
else
flag_1224 <= '0';
end if;
end if;
else
null;
end if;
end if;
end if;
end process;
--*****************************************************************************
-- Generate Scanning Code => Decoder(Scan Freq.=25M/2^17 = 190Hz)
with scan select
scan_seg <= "0001" when "00", -- min0
"0010" when "01", -- min1
"0100" when "10", -- hour0
"1000" when others; -- hour1
--*****************************************************************************
-- Multiplexer (4 to 1 MUX),Scan Freq.=25M/2^17 = 190Hz
with scan select
temp1 <= min0 when "00", -- min0
min1 when "01", -- min1
hour0 when "10", -- hour0
hour1 when others; -- hour1
--*****************************************************************************
-- BCD Decoder (High actived) Common-Anode 7-Segments Display
with temp1 select
--dpgfedcba
temp2 <= "00111111" when "0000", --0
"00000110" when "0001", --1
"01011011" when "0010", --2
"01001111" when "0011", --3
"01100110" when "0100", --4
"01101101" when "0101", --5
"01111100" when "0110", --6
"00000111" when "0111", --7
"01111111" when "1000", --8
"01100111" when "1001", --9
"01100010" when "1010", --Up (10)
"01010100" when "1011", --down(11)
"00000000" when others; --xx
--*****************************************************************************
-- dot-point : flash
process(clk)
begin
if(clk'event and clk = '1')then -- Postive-Edge Trigger
if(flag_sys = '1' and (scan = cnt_shift) and clk_1 = '1')then
seg_out <= (others => '0');
elsif(scan = "00" and clk_1 = '1') then
seg_out <= temp2 xor "10000000";
else
seg_out <= temp2;
end if;
end if;
end process;
--*****************************************************************************
end beh;

系統時間:2017-10-24 15:49:03
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